Semiconductor device and method of fabricating the same

ABSTRACT

A semiconductor device has a structure in which a gate electrode formed on a semiconductor substrate is buried in an interlevel insulating film so that the upper surface of the gate electrode is exposed, and an insulating film not containing boron and phosphorous is formed on this gate electrode. In this structure, the film thickness of the interlevel insulating film is small. This reduces the aspect ratio of a contact hole and improves the quality of burying of the contact hole. Since no interlevel insulating film which usually contains boron and phosphorous exists on the gate electrode, a shape change of the contact hole caused by annealing can be suppressed. This can improve the reliability of contact.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2000-088704, filed Mar.28, 2000, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a semiconductor device and amethod of fabricating the same and, more particularly, to a nonvolatilesemiconductor memory using a stacked gate structure MOS transistor as amemory cell transistor.

[0003] With the recent improvements of the semiconductor devicefabrication technologies, microfabrication of semiconductor memories isadvancing. As the density of semiconductor memories becomes ultra high,technologies for maintaining the reliability of such memories have alsobecome important.

[0004] The problems of conventional nonvolatile semiconductor memorieswill be explained below by taking a NAND flash EEPROM (ElectricallyErasable and Programmable Read Only Memory) as an example.

[0005]FIG. 1 is a plan view of a memory cell region of the NAND flashEEPROM. As shown in FIG. 1, shallow trench isolations (STI) 110 areformed on a silicon substrate 100 to extend in a direction in which bitlines BL run. Portions between adjacent shallow trench isolations 110are active areas (AA) 120 for forming elements.

[0006] Floating gates (FG) are selectively formed in the active areas120. Control gates (CG) of memory cell transistors and select gates (SG)of select transistors so run as to cover the floating gates FG and to beperpendicular to the active areas 120. In each active area 120, impuritydiffusion layers (not shown) serving as source and drain regions areselectively formed to sandwich the floating gates FG, the control gatesCG, and the select gates SG, thereby forming select transistors andmemory cell transistors.

[0007] A contact plug 130 is formed in the drain region of one selecttransistor, and the drain is connected to the bit line (BL) via thiscontact plug 130. The source of the other select transistor is connectedto the sources of adjacent select transistors by a local source line(not shown) formed by an impurity diffusion layer formed in the shallowtrench isolation 110.

[0008] A partial sectional structure of this NAND flash EEPROM will bedescribed below. FIGS. 2A and 2C are sectional views taken along lines2A-2A and 2C-2C, respectively, in a region 140 of FIG. 1. FIG. 2B is asectional view of a region corresponding to the line 2A-2A, in aperipheral region not shown in FIG. 1.

[0009] As shown in FIGS. 2A to 2C, silicon oxide films 150 and 160 areburied in trenches formed in the major surface of the semiconductorsubstrate 100, thereby forming the shallow trench isolations 110. A gateinsulating film 170 is formed on the active area 120 between adjacentshallow trench isolations 110. On this gate insulating film 170, thefloating gates FG made of polysilicon films 180 and 190, a floatinggate-control gate insulating film 200, and the control gates CG and theselect gates SG made of a polysilicon film 210 and a tungsten silicidefilm 220 are formed.

[0010] An impurity diffusion layer 230 is selectively formed in thesemiconductor substrate 100 between the gate electrodes in the aboveconstruction, thereby forming a select transistor and a memory celltransistor in a memory cell array region and a transistor in aperipheral region. In the select transistor and the transistor in theperipheral region, the floating gate-control gate insulating film 200 isremoved. Consequently, the two gate electrodes above and below thisfloating gate-control gate insulating film 200 are electricallyconnected.

[0011] In addition, silicon oxide films 240 and 250 are formed on thecontrol gates CG and the select gates SG. A silicon nitride film 260 isso formed as to cover the floating gates FG, the floating gate-controlgate insulating film 200, the control gates CG (or the select gates SG),and the silicon oxide films 240 and 250.

[0012] Furthermore, a BPSG interlevel insulating film 270 is formed tocover the entire surface. This interlevel insulating film 270 isplanarized by CMP to leave a residual film about 100 nm thick behind onthe control gates CG (or the select gates SG).

[0013] A silicon oxide film 280 is formed on this interlevel insulatingfilm 270. In this silicon oxide film 280, the bit line BL is formed inthe memory cell array region by a titanium film 290 and a tungsten film300, and is connected to the drain of the select transistor by thecontact plug 130.

[0014] In the peripheral region, a metal interconnecting layerconnecting to the transistor in this region is formed by the titaniumfilm 290 and the tungsten film 300. In this manner, the NAND flashEEPROM is fabricated.

[0015] The problems posed by the structure of the above conventionalnonvolatile semiconductor memory will be explained below with referenceto FIGS. 3A, 3B, 4A, and 4B. FIGS. 3A and 3B, or 4A and 4B are sectionalviews corresponding to FIGS. 2A and 2B, i.e., sectional views takenalong the bit line BL direction, of the contact portion between theselect transistor of the NAND flash EEPROM and the bit line and thecontact portion of the peripheral transistor.

[0016] In the conventional structure and fabrication method, the BPSGfilm 270 serving as an interlevel insulating film remains by a thicknessof about 100 nm on the control gates CG (the selector gates SG) owing tolimitations on the fabrication technology. However, the film thicknessof this BPSG film 270 sometimes increases because the controllability ofplanarization and film thickness adjustment of the BPSG film 270 is low.Since this increases the depth of contact holes as shown in FIGS. 3A and3B, a contact plug 130 made of a polysilicon film and the tungsten film300 cannot be well buried in these contact holes (regions 500). Thisleads to inferior contact.

[0017] Furthermore, the silicon oxide film 280 shrinks when annealing isperformed after the contact hole is formed in the peripheral region.This shrinkage causes the BPSG film 270 to reflow. As shown in FIGS. 4Aand 4B, this reflow of the BPSG film 270 deforms the shapes of thecontact holes (regions 510), leading to contact failures.

BRIEF SUMMARY OF THE INVENTION

[0018] It is an object of the present invention to provide a highlyreliable nonvolatile semiconductor memory in which changes in contacthole shape are prevented and contact failures are suppressed byimproving the quality of burying, and to provide a method of fabricatingthe same.

[0019] To achieve the above object, a semiconductor device according tothe first aspect of the present invention comprises

[0020] a semiconductor substrate,

[0021] a plurality of impurity diffusion regions, selectively formed onthe semiconductor substrate,

[0022] a plurality of insulated gate electrodes each formed on thesemiconductor substrate between two adjacent ones of the plurality ofimpurity diffusion regions,

[0023] a first insulating film formed on the semiconductor substrate tobury the plurality of gate electrodes so as to expose an upper surfaceof each gate electrode,

[0024] a second insulating film formed on the plurality of gateelectrodes and on the first insulating film and not substantiallycontaining boron and phosphorous, and

[0025] a conductive contact plug extending through the first and secondinsulating films and connecting to a predetermined one of the pluralityof impurity diffusion regions.

[0026] A nonvolatile semiconductor memory according to the second aspectof the present invention comprises

[0027] a semiconductor substrate,

[0028] a first gate insulating film formed on the semiconductorsubstrate,

[0029] a first gate electrode formed on the first gate insulating film,

[0030] a second gate insulating film formed on the first gate electrode,

[0031] a second gate electrode formed on the second gate insulating filmand at least partly overlapping the first gate electrode,

[0032] a first insulating film formed on the second gate electrode,

[0033] a second insulating film formed on at least side walls of astacked gate structure and on the semiconductor substrate, the stackedgate structure being formed by stacking the first gate insulating film,the first gate electrode, the second gate insulating film, the secondgate electrode, and the first insulating film,

[0034] a third insulating film formed on the semiconductor substrate soas to bury side wall portions of the stacked gate structure, and havingan upper surface reaching the first insulating film,

[0035] a fourth insulating film formed on the first and third insulatingfilms and not substantially containing boron and phosphorous, and

[0036] a conductive member buried in a contact hole reaching thesemiconductor substrate through the fourth, third, and second insulatingfilms.

[0037] A semiconductor device fabrication method according to the thirdaspect of the present invention comprises the steps of

[0038] forming a plurality of insulated gate electrodes on asemiconductor substrate,

[0039] forming a third insulating film on at least the plurality of gateelectrodes,

[0040] forming a first insulating film on the third insulating film andon the semiconductor substrate so as to bury regions between theplurality of gate electrodes,

[0041] planarizing the first insulating film by removal until the thirdinsulating film on the gate electrodes is exposed,

[0042] forming a second insulating film not substantially containingboron and phosphorous after the step of planarizing the first insulatingfilm,

[0043] forming a contact hole reaching the semiconductor substratethrough the second and first insulating films, and burying a conductivemember reaching the semiconductor substrate into the contact hole.

[0044] A nonvolatile semiconductor memory fabrication method accordingto the fourth aspect of the present invention comprises the steps of

[0045] forming a first gate insulating film on a semiconductorsubstrate,

[0046] forming a first gate electrode on the first gate insulating film,

[0047] forming a second gate insulating film on the first gateelectrode,

[0048] forming, on the second gate insulating film, a second gateelectrode at least partly overlapping the first gate electrode,

[0049] forming a first insulating film on the second gate electrode,

[0050] forming a second insulating film on a stacked gate structure andon the semiconductor substrate, the stacked gate structure being formedby stacking the first gate insulating film, the first gate electrode,the second gate insulating film, the second gate electrode, and thefirst insulating film,

[0051] forming a third insulating film on the semiconductor substrate soas to bury the stacked gate structure,

[0052] planarizing the third insulating film by reflow,

[0053] removing a surface of the third insulating film until the secondinsulating film on an upper surface of the stacked gate structure isreached,

[0054] forming a fourth insulating film on the third and secondinsulating films,

[0055] forming a contact hole reaching the semiconductor substratethrough the fourth, third, and second insulating films, and

[0056] burying a conductive member reaching the semiconductor substrateinto the contact hole.

[0057] The nonvolatile semiconductor memory of the present invention hasa structure in which no first insulating film is formed on a gateelectrode formed on a semiconductor substrate, and a second insulatingfilm not containing boron and phosphorous is formed on this gateelectrode. This structure is equivalent to decreasing the film thicknessof the first insulating film, i.e., of an interlevel insulating film.Accordingly, the aspect ratio of a contact hole of a semiconductordevice can be reduced, and this can improve the quality of burying ofthe contact hole. In addition, no first insulating film which usuallycontains boron and phosphorous exists on the gate electrode. So, a shapechange of the contact hole caused by annealing can be suppressed. Thiscan improve the reliability of contact.

[0058] In the semiconductor device fabrication method of the presentinvention, a first insulating film for burying a gate electrode isformed on a semiconductor substrate. After this first insulating film isallowed to reflow, the film is removed to substantially the uppersurface of the gate electrode. Removing the first insulating film tosubstantially the upper surface of the gate electrode is equivalent todecreasing the film thickness of an interlevel insulating film. So, theaspect ratio of a contact hole to be formed later can be reduced. In acontact plug formation step, therefore, the contact hole can be wellfilled with a conductive member. Also, since the first insulating filmdoes not exist on the gate electrode, a shape change of the contact holecaused by annealing can be suppressed. As a result, the reliability ofcontact can be improved.

[0059] Additional objects and advantages of the invention will be setforth in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention may be realized and obtained bymeans of the instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0060] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently preferredembodiments of the invention, and together with the general descriptiongiven above and the detailed description of the preferred embodimentsgiven below, serve to explain the principles of the invention.

[0061]FIG. 1 is a schematic plan view of a memory cell portion of aconventional NAND flash EEPROM;

[0062]FIG. 2A is a sectional view taken along a line 2A-2A in FIG. 1 (amemory cell region);

[0063]FIG. 2B is a sectional view taken along a line (not shown)corresponding to the line 2A-2A in FIG. 1, in a memory cell peripheralregion;

[0064]FIG. 2C is a sectional view taken along a line 2C-2C in FIG. 1(the memory cell region);

[0065]FIGS. 3A and 3B are views for explaining conventional bad contactburying, in which FIG. 3A is a sectional view corresponding to FIG. 2A,which shows a contact portion of a select transistor of the NAND flashEEPROM, and FIG. 3B is a sectional view corresponding to FIG. 2B, whichshows a contact portion of a peripheral circuit;

[0066]FIGS. 4A and 4B are views for explaining conventional contactbending, in which FIG. 4A is a sectional view corresponding to FIG. 2A,which shows a contact portion of a select transistor of the NAND flashEEPROM, and FIG. 4B is a sectional view corresponding to FIG. 2B, whichshows a contact portion of a peripheral circuit;

[0067]FIG. 5 is a circuit diagram of the major parts of a NAND flashEEPROM according to an embodiment of the present invention;

[0068]FIG. 6 is a plan view of a memory cell portion of the NAND flashEEPROM according to the embodiment of the present invention;

[0069]FIG. 7A is a sectional view taken along a line 7A-7A in FIG. 6 (amemory cell region);

[0070]FIG. 7B is a sectional view taken along a line (not shown)corresponding to the line 7A-7A in FIG. 6, in a memory cell peripheralregion;

[0071]FIG. 7C is a sectional view taken along a line 7C-7C in FIG. 6;

[0072] FIGS. 8 to 37, each of which includes three figures having asuffix “A”, “B”, or “C”, such as FIGS. 8A, 8B and 8C are sectional viewsshowing the steps in fabricating the NAND flash EEPROM according to theembodiment of the present invention in the order of the steps, in whichviews having suffixes “A”, “B”, and “C” are sectional viewscorresponding to FIGS. 7A, 7B, and 7C, respectively; and

[0073]FIG. 38 is a view for explaining an example in which the presentinvention is applied to a NOR flash EEPROM, which is a sectional viewtaken along the bit line direction of the NOR flash EEPROM.

DETAILED DESCRIPTION OF THE INVENTION

[0074] An embodiment of the present invention will be described belowwith reference to the accompanying drawings. In this description, thesame reference numerals denote the same parts in all views. In thisembodiment, a method of fabricating a semiconductor memory will beexplained by taking a NAND flash EEPROM as an example.

[0075]FIG. 5 is a circuit diagram showing a memory cell array and itspartial peripheral circuit (column selector) of the NAND flash EEPRPOMaccording to this embodiment. As shown in FIG. 5, this memory cell array1 of the NAND flash EEPROM includes a plurality of NAND cells 4 eachcomposed of, e.g., eight memory cell transistors 3-1 to 3-8 connected inseries between two select transistors 2-1 and 2-2.

[0076] The control gates of the memory cell transistors 3-1 to 3-8 ineach NAND cell 4 are connected to control gate lines CG1 to CG8. Theselect gates of the select transistors are connected to select gatelines SG1 and SG2. These select gate lines SG1 and SG2 and control gatelines CG1 to CG8 are connected to a row decoder 5.

[0077] This row decoder 5 selectively drives the control gate lines CG1to CG8 and the select gate lines SG1 and SG2. The drain of the selecttransistor 2-1 is connected to one of bit lines BLi (i=1, 2, . . . )These bit lines BLi are connected to a column selector 6.

[0078] The column selector 6 has a plurality of transistors 7-1, 7-2, .. . . One end of the current path of each of these transistors 7-1, 7-2,. . . , is connected to a corresponding one of the bit lines BL1, BL2, .. . . The gates of these transistors are connected to column-selectlines CSL1 to CSL4. These column-select lines CSL1 to CSL4 are connectedto a column decoder 8.

[0079] This column decoder 8 selectively drives the column-select linesCSL1 to CSL4. When the transistors 7-1 to 7-4 connected to thesecolumn-select lines CSL1 to CSL4 are selectively driven, one of the bitlines BL1 to BL4 is connected to a read/write node 9. This read/writenode 9 is connected to a read-out circuit and a write-in circuit(neither is shown).

[0080] The source of the select transistor 2-2 in the NAND cell 4 isconnected to a common local source line SL and connected to a sourcedecoder via a global source line (not shown).

[0081]FIG. 6 is a plan view showing a partial pattern of a memory cellarray region in the above NAND flash EEPROM. As shown in FIG. 6, shallowtrench isolations (STI) 11 are formed on a silicon substrate 10 in adirection in which the bit lines BL run. Portions between these shallowtrench isolations 11 are active areas (AA) 12 for forming elements.

[0082] Floating gates FG are selectively formed in the active areas 12.Control gates CG and select gates SG so run as to cover these floatinggates FG and to be perpendicular to the active areas 12. In the siliconsubstrate 10 in each active area 12, impurity diffusion layers (notshown) serving as source and drain regions are formed to sandwich thefloating gates FG, the control gates CG, and the select gates SG,thereby forming the select transistors 2-1 and 2-2 and the memory celltransistors 3-1 to 3-8.

[0083] The drain region of the select transistor 2-1 is connected to thebit line BL via a contact plug 13. The source of the select transistor2-2 is connected to the source of an adjacent select transistor by thelocal source line SL formed by an impurity diffusion layer formed in theshallow trench isolation 11.

[0084] A partial sectional structure of the above NAND flash EEPROM willbe described below. FIG. 7A is a sectional view taken along a line 7A-7Ain FIG. 6. FIG. 7C is a sectional view taken along a line 7C-7C. FIG. 7Bis a sectional view of a region (not shown) corresponding to the line7A-7A in FIG. 6, in a peripheral region. An example of the peripheralregion is a column selector.

[0085] As shown in FIGS. 7A to 7C, silicon oxide films 15 and 16 areburied in trenches formed in the major surface of the silicon substrate10, thereby forming the shallow trench isolations 11. A gate insulatingfilm 17 (first gate insulating film) is formed on the active area 12between these shallow trench isolations 11. On this gate insulating film17, the floating gates FG (first gate electrodes) made of polysiliconfilms 18 and 19, a floating gate-control gate insulating film 20 (secondgate insulating film) made of a multilayered ONO (Oxide-Nitride-Oxide)film including silicon oxide and silicon nitride films, and the controlgates CG or the select gates SG (second gate electrodes) made of apolysilicon film 21 and a tungsten silicide film 22 are formed.

[0086] In the semiconductor substrate 10 between the gate electrodes inthe above structure, impurity diffusion layers 23 serving as a sourceand drain are selectively formed. In this manner, the select transistors2-1 and 2-2 and the memory cell transistors 3-1 to 3-8 in the memorycell region and the transistors in the peripheral region are formed.

[0087] In the select transistor and the transistor in the peripheralregion, at least a portion of the floating gate-control gate insulatingfilm 20 is removed. In this way, the two gates above and below thefloating gate-control gate insulating film 20 are electrically connectedin a region (not shown).

[0088] Silicon oxide films 24 and 25 are formed on the control gates CG(selector gates SG). A silicon nitride film 26 (second insulating film)is formed on the entire surface so as to cover the floating gates FG,the floating gate-control gate insulating film 20, the control gates CG(select gates SG), and the silicon oxide films 24 and 25.

[0089] Also, an interlevel insulating film 27 (third insulating film) isso formed as to bury portions between the adjacent gate electrodes. Asilicon oxide film 28 (fourth insulating film) is formed on thisinterlevel insulating film 27 and the silicon nitride film 26.

[0090] In the silicon oxide film 28, the bit line BL made of a titaniumfilm 29 and a tungsten film 30 is formed in the memory cell arrayregion, and a metal interconnection connecting to the transistors isformed in the peripheral region. The contact plug 13 connecting to thebit line BL is so formed as to connect to the drain region of the selecttransistor.

[0091] A second interlevel insulating film 31 covers the entire surfaceof the above structure. A passivation film 32 and a coating material 33are formed on this second interlevel insulating film 31, thereby formingthe NAND flash EEPROM.

[0092] A method of fabricating the NAND flash EEPROM with the aboveconstruction will be described below with reference to FIGS. 8A to 8Cand 37A to 37C. These views are sectional views showing the fabricationsteps of the NAND flash EEPROM in the order of the steps. Views having asuffix A correspond to FIG. 7A, and they are sectional views taken alongthe bit line direction. Views having a suffix C correspond to FIG. 7C,and they are sectional views taken along the word line direction. Viewshaving a suffix B correspond to FIG. 7B, and they are sectional viewstaken along the bit line direction in the peripheral region.

[0093] As shown in FIGS. 8A to 8C, an 8-nm thick silicon oxide filmserving as a gate insulating film 17 is formed on a silicon substrate 10by thermal oxidation or the like. On this gate insulating film 17, a60-nm thick polysilicon film 18 is formed by low pressure CVD (ChemicalVapor Deposition) or the like. Although the gate insulating film 17 canremain as a silicon oxide film, it can also be turned into an oxynitridefilm by nitriding and oxidation using NH₃ gas or the like.

[0094] Subsequently, as shown in FIGS. 9A to 9C, a 70-nm thick siliconnitride film 34 and a 230-nm thick silicon oxide film 35 are formed onthe polysilicon film 18 by low pressure CVD or the like. Pyrogenicoxidation is performed at 850° C. for 30 min.

[0095] The entire surface is coated with a photoresist 36-1, and thisphotoresist 36-1 is patterned as shown in FIGS. 10A to 10C byphotolithography. This photoresist 36-1 is used as a mask to performanisotropic etching such as RIE (Reactive Ion Etching), therebyprocessing the silicon oxide film 35 and the silicon nitride film 34.The photoresist 36-1 is then removed by processing using O₂-plasma and asolution mixture of sulfuric acid and hydrogen peroxide (FIGS. 11A to11C).

[0096] As shown in FIGS. 12A to 12C, the polysilicon film 18, thesilicon oxide film 17, and the silicon substrate 10 are sequentiallyetched by RIE or the like using the silicon oxide film 35 and thesilicon nitride film 34 as masks, thereby forming trenches 37 forforming shallow trench isolations.

[0097] Annealing is then performed in an oxidizing ambient at 1,000° C.Consequently, as shown in FIGS. 13A to 13C, a 6-nm thick silicon oxidefilm 15 is formed on the surfaces of the silicon substrate 10 exposed tothe surfaces of the trenches 37. This silicon oxide film 15 rounds thecorners of the trenches 37 to thereby prevent concentration of stressand the like to these corners.

[0098] In addition, a 430-nm thick silicon oxide film 16 is formed onthe entire surface by an HDP (High Density Plasma) method or the like.As a result, the trenches 37 are filled with this silicon oxide film 16.Subsequently, the silicon oxide films 16 and 35 are planarized by CMPusing the silicon nitride film 34 as a stopper, thereby completingshallow trench isolations 11 as shown in FIGS. 14A to 14C.

[0099] As shown in FIGS. 15A to 15C, the silicon oxide film 16 is etchedby 20 nm by an HF solution. Then, as shown in FIGS. 16A to 16C,phosphoric acid processing is performed at 150° C. for 40 min toselectively remove the silicon nitride film 34.

[0100] After that, as shown in FIGS. 17A to 17C, a 100-nm thickpolysilicon film 19 and a 230-nm thick silicon oxide film 38 are formedin this order by low pressure CVD.

[0101] As shown in FIGS. 18A to 18C, the entire surface is coated with aphotoresist 36-2, and this photoresist 36-2 is patterned byphotolithography. The silicon oxide film 38 is processed by RIE or thelike using this photoresist 36-2 as a mask. The resist 36-2 is thenremoved by processing using O₂-plasma and a solution mixture of sulfuricacid and hydrogen peroxide.

[0102] A 70-nm thick silicon oxide film 39 is formed on the entiresurface by low pressure CVD or the like. After that, as shown in FIGS.19A to 19C, this silicon oxide film 39 is etched by whole-surface etchback so as to remain only on the side walls of the silicon oxide film38.

[0103] As shown in FIGS. 20A to 20C, portions of the polysilicon film 19and the silicon oxide film 16 are removed by RIE using the silicon oxidefilms 38 and 39 as masks. After that, the silicon oxide films 38 and 39as mask materials are removed by using O₂-plasma and a solution mixtureof sulfuric acid and hydrogen peroxide, thereby completing a floatinggate FG made of the polysilicon films 18 and 19.

[0104] As shown in FIGS. 21A to 21C, a 17-nm thick floating gate-controlgate insulating film 20 is formed on the entire surface by low pressureCVD. For example, this floating gate-control gate insulating film 20 isa three-layered ONO film having a silicon oxide film (SiO₂: 5 nm),silicon nitride film (SiN: 7 nm), and silicon oxide film (SiO₂: 5 nm).Note that the floating gate-control gate insulating film 20 can also bea simple silicon oxide film or a two-layered ON or NO film composed of asilicon oxide film and silicon nitride film.

[0105] This floating gate-control gate insulating film 20 is removedfrom partial regions (not shown) of prospective regions of a selecttransistor and a transistor in a peripheral region. It is of course alsopossible to remove the floating gate-control gate insulating film 20from the entire prospective regions.

[0106] Subsequently, as shown in FIGS. 22A to 22C, an 8-nm thickpolysilicon film 21 and a 50-nm thick tungsten silicide film 22 areformed on the floating gate-control gate insulating film 20 by lowpressure CVD and PVD (Physical Vapor Deposition), respectively.Furthermore, a 230-nm thick silicon oxide film 24 is formed on thetungsten silicide film 22 by low pressure CVD.

[0107] The entire surface is coated with a photoresist (not shown), andthis photoresist is patterned into the patterns of a control gate CG ofa memory cell transistor and a select gate SG of a select transistor byphotolithography. After the silicon oxide film 24 is patterned by RIEusing this photoresist as a mask, the photoresist is removed.

[0108] RIE using the silicon oxide film 24 patterned in the above stepas a mask is then performed to etch the tungsten silicide film 22, thepolysilicon film 21, the floating gate-control gate insulating film 20,and the polysilicon films 19 and 18, thereby completing two-layeredgates as shown in FIGS. 23A to 23C.

[0109] More specifically, the gate electrodes of a memory celltransistor and select transistor are formed by a two-layered structureincluding the floating gate FG made of the polysilicon films 18 and 19and the control gate CG (select gate SG) made of the polysilicon film 21and the tungsten silicide film 22. As described previously, however, thefloating gate FG and the select gate SG are electrically connected in aregion (not shown) of the select transistor.

[0110] Annealing is first performed in a nitrogen ambient at 800° C. andthen in an oxidizing ambient at 1,000° C., forming a 10-nm thick siliconoxide film 25 on the silicon oxide film 24. Note that these films 24 and25 can also be silicon nitride films, instead of silicon oxide films.

[0111] After that, an impurity is doped into prospective regions of asource and drain by ion implantation, thereby selectively formingimpurity diffusion layers 23. Annealing is performed at 1,050° C. for 30sec to activate the doped impurity.

[0112] Subsequently, a 40-nm thick silicon nitride film 26 is formed onthe entire surface by low pressure CVD. By the steps described so far, astructure shown in FIGS. 24A to 24C is formed, and a memory cell arrayregion and a MOS transistor in a peripheral region of a NAND flashEEPROM are completed.

[0113] As shown in FIGS. 25A to 25C, a 300-nm thick interlevelinsulating film 27 as a BPSG film having high step coverage is formed onthe entire surface by normal pressure CVD. This BPSG film 27 is causedto reflow by performing annealing in a nitrogen ambient at 800° C. for30 min, thus planarizing the surface (FIGS. 26A to 26C). However, if astep is present on the underlying layer on which the BPSG film is to bedeposited and if this step is large, even the BPSG film having high stepcoverage is sometimes unable to well cover the step to form a pit 48.

[0114] As shown in FIGS. 27A to 27C, therefore, a 300-nm thick BPSG film40 is additionally deposited. This BPSG film 40 is allowed to reflow tofill the pit 48 formed in the BPSG film 27 (FIGS. 28A to 28C).

[0115] As shown in FIGS. 29A to 29C, these BPSG films 27 and 40 arepolished by CMP using the silicon nitride film 26 as a stopper. Afterthat, the surfaces of the BPSG films 27 and 40 are planarized byperforming annealing in a nitrogen ambient at 800° C. for 15 min.Subsequently, the density of these BPSG films 27 and 40 is increased byperforming annealing in a nitrogen ambient at 950° C. for 10 sec.

[0116] As shown in FIGS. 30A to 30C, a 350-nm thick silicon oxide film28 is formed on the entire surface by plasma CVD. The surface of thissilicon oxide film 28 is coated with a photoresist (not shown). Thisphotoresist is patterned by photolithography into the formation patternof a contact hole for contacting the impurity diffusion layer 23 of theselect transistor.

[0117] RIE using the patterned photoresist as a mask is performed tofirst etch the silicon oxide film 28 and the BPSG films 27 and 40. Afterthe photoresist is removed, RIE using the silicon oxide film 28 as amask is performed to etch the silicon nitride film 26 and the gateinsulating film 17, thereby forming a contact hole 41 (FIGS. 31A to31C). After that, the reaction product deposited on the side walls ofthe contact hole 41 when RIE is performed is removed by O₂-plasma and asolution mixture of sulfuric acid and hydrogen peroxide.

[0118] As shown in FIGS. 32A to 32C, a 300-nm thick polysilicon film 42is formed on the entire surface by low pressure CVD to fill the contacthole 41.

[0119] After that, as shown in FIGS. 33A to 33C, the polysilicon film 42is etched to a desired height in the contact hole 41 by CDE (ChemicalDye Etching). The residual polysilicon film 42 is annealed in a nitrogenambient at 950° C. for 10 sec to form a contact plug 13.

[0120] The surface of the silicon oxide film 28 is then coated with aphotoresist (not shown). This photoresist is patterned into theformation pattern of a contact hole for contacting the impuritydiffusion layer 23 of the transistor in a peripheral circuit. RIE usingthe patterned photoresist as a mask is performed to etch the siliconoxide film 28 and the BPSG film 27. After the photoresist is removed,RIE using the silicon oxide film 28 as a mask is performed to etch thesilicon nitride film 26 and the gate insulating film 17, thereby forminga contact hole 43 as shown in FIGS. 34A to 34C. After that, the reactionproduct deposited on the side walls of the contact hole 43 when RIE isperformed is removed by O₂-plasma and a solution mixture of sulfuricacid and hydrogen peroxide.

[0121] After that, the surface of the silicon oxide film 28 is coatedwith a photoresist (not shown). The silicon oxide film 28 is thenpatterned by lithography and etching into the wiring pattern of a bitline connecting to the impurity diffusion layer of the select transistorand into the wiring pattern of a line connecting to the impuritydiffusion layer of the transistor in the peripheral circuit. Thephotoresist and the reaction product deposited by the etching areremoved to obtain a structure shown in FIGS. 35A to 35C. In addition, animpurity is doped by ion implantation into the semiconductor substrateat the bottom of the contact hole 43. The doped impurity is activated byRTA (Rapid Thermal Annealing) performed in a nitrogen ambient at 950° C.

[0122] As shown in FIGS. 36A to 36C, a 300-nm thick titanium film 29 anda 400-nm tungsten film 30 are formed in this order on the entire surfaceby PVD.

[0123] As shown in FIGS. 37A to 37C, the titanium film 29 and thetungsten film 30 are planarized by CMP until the silicon oxide film 28in a region where no bit line is to be formed. Annealing is thenperformed in a hydrogen-containing nitrogen ambient at 400° C. for 30min.

[0124] After that, a BPSG film 31 as a second interlevel insulating filmis deposited on the entire surface. A metal interconnecting layer isfurther formed, as needed, on this BPSG film 31. On the metalinterconnecting layer and the BPSG film 31, a silicon nitride film isformed as a passivation film 32 by plasma CVD or the like. To improvethe reliability of the metal interconnecting layer, a PSG (PhosphorousSilicate Glass) film formed by thermal CVD or a silicon oxide filmformed by plasma CVD may also be interposed between the metalinterconnecting layer and the passivation film 32. After that, a coatingmaterial 33 for protecting the semiconductor memory is formed on theentire surface, and holes are formed in a region where bonding pads arepositioned, thereby completing the semiconductor memory as shown inFIGS. 7A to 7C.

[0125] In the nonvolatile semiconductor memory and its fabricationmethod as described above, the BPSG films 27 and 40 are formed asinterlevel insulating films so as to cover a MOS transistor on thesilicon substrate 10, and these BPSG films 27 and 40 are then polisheduntil the silicon nitride film 26 on the control gates CG (select gatesSG) is exposed. Since this can decrease the film thicknesses of theinterlevel insulating films, the aspect ratios of the contact holes 41and 43 can be reduced. Accordingly, these contact holes 41 and 43 can bewell filled with conductive materials in the subsequent steps.

[0126] Also, the BPSG film 27 does not exist on the control gates CG(select gates SG), so the reflow of the BPSG film 27 caused by theshrinkage of the silicon oxide film 28 upon annealing can be minimized.Since this can suppress shape changes of the contact holes 41 and 43, itis possible to prevent contact failures and improve the reliability ofthe nonvolatile semiconductor memory.

[0127] Note that the steps of polishing the BPSG films 27 and 40 neednot be terminated when the silicon nitride film 26 on the control gatesCG (select gates SG) is exposed; the silicon nitride film 26 can bepartly or entirely removed at once.

[0128] Furthermore, the above embodiment is explained by taking a NANDflash EEPROM as an example. However, the present invention is naturallyapplicable to a NOR flash EEPROM as well as to a NAND memory.

[0129]FIG. 38 is a sectional view, taken along the bit line direction,of a memory cell array region of a NOR flash EEPROM. As shown in FIG.38, memory cell transistors are formed on a semiconductor substrate 10so as to connect in series by sharing adjacent impurity diffusion layers23. A BPSG film 27 is formed between adjacent gates of these memory celltransistors, and a silicon oxide film 28 is formed on this BPSG film 27and a silicon nitride film 26. Contact plugs 13 are so formed to connectto the drain regions of the memory cell transistors. These contact plugs13 are connected to a common bit line BL made of a titanium film 29 anda tungsten film 30. As described above, the BPSG film 27 covering thememory cell transistors is not formed on control gates CG, so the aspectratio of contact holes can be reduced. Accordingly, effects similar tothose explained in the above-mentioned NAND flash EEPROM can beobtained.

[0130] The present invention is, of course, applicable not only to aflash EEPROM but also to semiconductor memories such as a DRAM (DynamicRandom Access Memory) having trench or stacked capacitors and an EPROMhaving a two-layered gate structure. Furthermore, the present inventioncan be extensively applied not only to semiconductor memories but alsoto other semiconductor devices and their fabrication methods.

[0131] As has been described above, the present invention can provide anonvolatile semiconductor memory and a method of fabricating the same,capable of preventing a shape change of a contact hole and improving thequality of burying by reducing the aspect ratio of the contact hole,thereby improving the reliability of interconnections.

[0132] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate; a plurality of impurity diffusion regionsselectively formed on said semiconductor substrate; a plurality ofinsulated gate electrodes each formed on said semiconductor substratebetween two adjacent ones of said plurality of impurity diffusionregions; a first insulating film formed on said semiconductor substrateto bury said plurality of gate electrodes so as to expose an uppersurface of each of said gate electrodes; a second insulating film formedon said plurality of gate electrodes and on said first insulating filmand not substantially containing boron and phosphorous; and a conductivecontact plug extending through said first and said second insulatingfilm and connecting to a predetermined one of said plurality of impuritydiffusion regions.
 2. The device according to claim 1 , where said firstinsulating film is a silicon oxide film containing boron andphosphorous, and said second insulating film is a silicon oxide film. 3.The device according to claim 1 , further comprising a third insulatingfilm formed between said plurality of gate electrodes and said first andsaid second insulating film, and between a major surface of saidsemiconductor substrate between said plurality of gate electrodes andsaid first insulating film.
 4. The device according to claim 3 , whereinsaid third insulating film is a member selected from the groupconsisting of a silicon oxide film and silicon nitride film.
 5. Thedevice according to claim 3 , wherein an upper surface of said firstinsulating film is substantially flush with an upper surface of saidthird insulating film.
 6. A nonvolatile semiconductor memory comprising:a semiconductor substrate; a first gate insulating film formed on saidsemiconductor substrate; a first gate electrode formed on said firstgate insulating film; a second gate insulating film formed on said firstgate electrode; a second gate electrode formed on said second gateinsulating film and at least partly overlapping said first gateelectrode; a first insulating film formed on said second gate electrode;a second insulating film formed on at least side walls of a stacked gatestructure and on said semiconductor substrate, said stacked gatestructure being formed by stacking said first gate insulating film, saidfirst gate electrode, said second gate insulating film, said second gateelectrode, and said first insulating film; a third insulating filmformed on said semiconductor substrate so as to bury side wall portionsof said stacked gate structure, and having an upper surface reachingsaid first insulating film; a fourth insulating film formed on saidfirst and third insulating films and not substantially containing boronand phosphorous; and a conductive member buried in a contact holereaching said semiconductor substrate through said second, said third,and said fourth insulating film.
 7. The memory according to claim 6 ,wherein at least a partial region of an upper surface of said firstinsulating film reaches said fourth insulating film.
 8. The memoryaccording to claim 6 , wherein said third insulating film is a siliconoxide film containing boron and phosphorous.
 9. The memory according toclaim 6 , wherein said first insulating film is a member selected fromthe group consisting of a silicon oxide film and a silicon nitride film,said second insulating film is a silicon nitride film, and said fourthinsulating film is a silicon oxide film.
 10. The memory according toclaim 6 , wherein an upper surface of said third insulating film isflush with an upper surface of said first insulating film.
 11. Asemiconductor device fabrication method comprising the steps of: forminga plurality of insulated gate electrodes on a semiconductor substrate;forming a third insulating film on at least the plurality of gateelectrodes; forming a first insulating film on the third insulating filmand on the semiconductor substrate so as to bury regions between theplurality of gate electrodes; planarizing the first insulating film byremoval until the third insulating film on the gate electrodes isexposed; forming a second insulating film not substantially containingboron and phosphorous after the step of planarizing the first insulatingfilm; forming a contact hole reaching the semiconductor substratethrough the first and the second insulating film; and burying aconductive member reaching the semiconductor substrate into the contacthole.
 12. The method according to claim 11 , wherein the step of formingthe third insulating film comprises the step of forming a siliconnitride film.
 13. The method according to claim 11 , wherein the step offorming the first insulating film comprises the step of forming asilicon oxide film containing boron and phosphorous.
 14. The methodaccording to claim 11 , wherein the step of forming the secondinsulating film comprises the step of forming a silicon oxide film notsubstantially containing boron and phosphorous.
 15. A nonvolatilesemiconductor memory fabrication method comprising the steps of: forminga first gate insulating film on a semiconductor substrate; forming afirst gate electrode on the first gate insulating film; forming a secondgate insulating film on the first gate electrode; forming, on the secondgate insulating film, a second gate electrode at least partlyoverlapping the first gate electrode; forming a first insulating film onthe second gate electrode; forming a second insulating film on a stackedgate structure and on the semiconductor substrate, the stacked gatestructure being formed by stacking the first gate insulating film, thefirst gate electrode, the second gate insulating film, the second gateelectrode, and the first insulating film; forming a third insulatingfilm on the semiconductor substrate so as to bury the stacked gatestructure; planarizing the third insulating film by reflow; removing thesurface of the third insulating film until the second insulating film onthe upper surface of the stacked gate structure is reached; forming afourth insulating film on the second and the third insulating film;forming a contact hole reaching the semiconductor substrate through thesecond, the third, and the fourth insulating film; and burying aconductive member reaching the semiconductor substrate into the contacthole.
 16. The method according to claim 15 , further comprising, afterthe step of removing the surface of the third insulating film until thesecond insulating film on an upper surface of the stacked gate structureis reached, the step of; removing the second and the third insulatingfilm to expose at least a partial region of the first insulating film onthe stacked gate structure.
 17. The method according to claim 15 ,wherein the step of forming the first insulating film comprises the stepof forming a film selected from the group consisting of a silicon oxidefilm and a silicon nitride film.
 18. The method according to claim 15 ,wherein the step of forming the second insulating film comprises thestep of forming a silicon nitride film.
 19. The method according toclaim 15 , wherein the step of forming the third insulating filmcomprises the step of forming a silicon oxide film containing boron andphosphorous.
 20. The method according to claim 15 , wherein the step offorming the fourth insulating film comprises the step of forming asilicon oxide film.